Methods of processing semiconductor wafer and producing IC card, and carrier

ABSTRACT

The semiconductor wafer is made thin without any cracks and warp under good workability. The semiconductor wafer thinning process includes the first step of preparing a carrier  1  formed of a base  1   a  and a suction pad  1   b  provided on one surface of the base  1   a  or formed of a base film with an adhesive, the second step of bonding a semiconductor wafer to the carrier  1  in such a manner that a rear surface of the semiconductor wafer  2  with no circuit elements formed therein is opposite to the carrier to form a wafer composite  10,  and the third step of holding the carrier of the wafer composite  10  with its semiconductor wafer  2  side up and spin-coating an etchant on the rear surface of the semiconductor wafer  2  thereby to make the semiconductor wafer  2  thin.

TECHNICAL FIELD

[0001] The present invention relates to semiconductor wafer processingtechniques, and particularly to a technique effective for use inhandling semiconductor wafers when the semiconductor wafers areprocessed to a very small thickness of 100 μm or below.

BACKGROUND ART

[0002] Now, in the semiconductor devices required to be thin as well ashigh density and small size, such as semiconductor devices applied to ICcards, thinner packages than the usual ones are used, such as TQFP (thinquad flat package) and TSOP (thin small outline package). In order tomanufacture such packages, it is necessary to make the semiconductorwafers particularly thin. Here, the known techniques for making thesemiconductor wafers thin, as for example described in “PRACTICALLECTURES VlSI PACKAGING TECHNOLOGY (the second volume)” published byNIKKEI BP Co., Ltd. on May 31, 1993, pp. 12 to 14, are three types ofgrinding, chemical etching and lapping. As in the publication, thegrinding is the technique for grinding the rear surface of asemiconductor wafer with a diamond grindstone, the etching is thetechnique for etching the rear surface of a semiconductor wafer with amixture of chiefly fluoric acid and nitric acid while the semiconductorwafer is being rotated with high speed, and the lapping is the techniquefor grinding the rear surface of a semiconductor wafer with abrasivegrains.

[0003] The thinning process by the grinding or lapping is able to grindsemiconductor wafers of general thickness, or about 625 μm (or 725 μm)to a thickness of about 300 μm, but has a difficulty when trying togrind to a thickness of, for example, 100 μm or below because thesemiconductor wafer might be cracked even under strict care whenremoving it from the grinder. Even if the wafer is not cracked, it isremarkably warped depending on the stress in the passivation film on thewafer surface and the internal stress of the wafer. This warp causesoperational problems in the following processes such as dicing. Inaddition, it is difficult to process large-diameter semiconductorwafers, or 12-inch or above wafers to a specified level of flatness anduniformity.

[0004] Moreover, in the thinning process by etching, since the wafer isrotated at high speed, an excessive stress is exerted on thesemiconductor wafer by the pins that hold its outer peripheral portionat a plurality of locations, thus breaking the wafer. Furthermore, awarp will occur due to the internal stress as in the grinding.

[0005] In order to solve the above problems, the inventors have found tofix the semiconductor wafer to a certain support base with tape andprocess it after various examinations. However, normal tape is alsodiscarded after use in the process of each wafer, thus increasing thecost, or causing a new problem.

[0006] Accordingly, it is an object of the invention to provide atechnique capable of making semiconductor wafers thin without any crackby solving the above technical problems.

[0007] It is another object of the invention to provide a techniquecapable of making semiconductor wafers thin under easy operation.

[0008] It is still another object of the invention to provide atechnique capable of making semiconductor wafers thin without any warp.

[0009] It is further object of the invention to provide a techniquecapable of making semiconductor wafers thin at low cost.

[0010] The features of the invention, and the above objects of theinvention together with other objects will be best understood by thefollowing description, taken in conjunction with the accompanyingdrawings.

DISCLOSURE OF INVENTION

[0011] A typical one of the inventions disclosed in this applicationwill be described briefly as below.

[0012] The semiconductor wafer processing method according to theinvention includes a first step of preparing a plate-like or film-shapedcarrier that is formed of a base and an adhesive member provided on onesurface of the base, a second step of producing a wafer composite bybonding a semiconductor wafer to the carrier in such a manner that therear surface of the wafer with no circuit elements formed therein isopposite to the carrier, and a third step of making the semiconductorwafer thin by spin-coating an etchant on the rear surface of thesemiconductor wafer of the wafer composite that is supported with itssemiconductor wafer side up.

[0013] In this semiconductor wafer processing method, the semiconductorwafer of the wafer composite is made to have a larger diameter than thecarrier so that all the outer peripheral edge of the semiconductor waferoverhangs from the carrier when the wafer composite is formed by bondingthe wafer on the carrier. In the third step, the semiconductor wafer canbe thinned while a gas is being blown from below against the wafercomposite. In addition, the semiconductor wafer may be made to have adiameter equal to or smaller than the carrier so that the peripheraledge of the wafer does not overhang from the carrier when the wafercomposite is formed.

[0014] Moreover, after the semiconductor wafer is thinned by the thirdstep, a fourth step and a fifth step may be provided. The fourth step isfor sticking the rear side of the wafer on a dicing sheet and peelingoff the carrier, and the fifth step is for dicing the semiconductorwafer on the dicing sheet into individual semiconductor chips.

[0015] The semiconductor wafer processing method of the inventionincludes a first step of preparing a semiconductor wafer with apassivation film formed on its main surface in which circuit elementsare already built, a second step of preparing a plate-like or film-likecarrier that is formed of a base and an adhesive member provided on onesurface of the base, a third step of producing a wafer composite bybonding the semiconductor wafer to the carrier in such a manner that therear surface of the wafer with no circuit elements formed therein isopposite to the carrier, and a fourth step of holding the wafercomposite with its semiconductor wafer side up and spin-coating anetchant on the rear surface of the semiconductor wafer thereby to thinthe semiconductor wafer. In this case, after thinning the semiconductorwafer at the fourth step, it is possible to add a fifth step ofattaching the rear surface of the semiconductor onto a dicing sheet andpeeling off the carrier from the wafer composite, and a sixth step ofdicing the semiconductor wafer left on the dicing sheet into individualsemiconductor chips.

[0016] The IC card producing method according to the invention includesa first step of preparing a plate-like or film-like carrier that isformed of a base and an adhesive member provided on one side of thebase, a second step of producing a wafer composite by bonding asemiconductor wafer to the carrier in such a manner that the rearsurface of the wafer with no circuit elements formed therein is oppositeto the carrier, a third step of holding the wafer composite with itssemiconductor wafer side up and spin-coating an etchant on the rearsurface of the semiconductor wafer thereby to thin the semiconductorwafer, a fourth step of attaching the thinned rear surface of thesemiconductor wafer to a dicing sheet and peeling off the carrier fromthe wafer composite, a fifth step of dicing the semiconductor wafer lefton the dicing sheet into individual semiconductor chips, a sixth step ofreducing or loosing or losing the adhesion of the dicing sheet, aseventh step of mounting one or ones of the semiconductor chips on acard substrate at chip-mounting positions, and an eighth step ofproducing an IC card by using the card substrate with the semiconductorchip or chips mounted.

[0017] According to the invention, there is provided an IC cardproducing method including a first step of preparing a semiconductorwafer with a passivation film formed on its main surface in whichcircuit elements are already built, a second step of preparing aplate-like or film-like carrier that is formed of a base and an adhesivemember provided on one surface of the base, a third step of producing awafer composite by bonding a semiconductor wafer to the carrier in sucha manner that the rear surface of the wafer with no circuit elementsformed therein is opposite to the carrier, a fourth step of holding thewafer composite with its semiconductor wafer side up and spin-coating anetchant on the rear surface of the semiconductor wafer thereby to thinthe semiconductor wafer, a fifth step of attaching the thinned rear sideof the semiconductor wafer to a dicing sheet and peeling off the carrierfrom the wafer composite, a sixth step of dicing the semiconductor waferleft on the dicing sheet into individual semiconductor chips, a seventhstep of reducing or loosing or losing the adhesion of the dicing sheet,an eighth step of mounting one or ones of the semiconductor chips on acard substrate at chip-mounting positions, and a ninth step of producingan IC card by using the card substrate with the semiconductor chip orchips mounted.

[0018] When bumps are formed at the chip electrodes of the semiconductorwafer in the IC card producing methods of the invention, the thicknessof the adhesive member provided on the base should be equal to or largerthan the height of the bumps. In addition, at the seventh step, it isdesirable to directly mount the semiconductor chips on the cardsubstrate from the dicing sheet.

[0019] Moreover, the carrier in the invention is used in thesemiconductor wafer processing method, and its adhesive member comprisesan elastically flexible suction pad for sucking the semiconductor waferby vacuum. In this carrier, the suction pad may have a size enough tosuck substantially all region of one surface of the semiconductor wafer.In addition, it may be formed in a ring shape along the outer peripheryof the semiconductor wafer. Also, a plurality of such suction pads maybe provided on all the region of one surface of the base in order tohold the semiconductor wafer at a plurality of locations.

[0020] In addition, the carrier in the invention is used in thesemiconductor wafer processing method, and its adhesive member comprisesa suction groove that is formed in the base to be communicated with avacuum hole connected to a vacuum pump so that the semiconductor waferis sucked by vacuum and peeled off from the carrier by restoring toatmospheric pressure.

[0021] Also, the carrier in the invention is used in the semiconductorwafer processing method according to the invention, and its adhesivemember is constituted by a plurality of suction holes which are formedin one surface of the base at different locations to be communicatedwith a vacuum hole connected to a vacuum pump so that the semiconductorwafer is sucked by negative pressure and peeled off from the carrier byrestoring to atmospheric pressure.

[0022] Moreover, the carrier in the invention is used in thesemiconductor wafer processing method according to the invention, andits adhesive member comprises a porous member that has a great number ofsmall holes and is provided on one surface of the base for the smallholes to be communicated with a vacuum hole connected to a vacuum pumpso that the semiconductor wafer is sucked by vacuum and that it ispeeled off from the carrier by restoring to atmospheric pressure.

[0023] Also, the carrier in the invention is used in the semiconductorwafer processing method according to the invention, and its adhesivemember includes an exfoliation portion coplanar with the base to form aplurality of small recesses, and gelled silicone interposed between thepeeling portion and the semiconductor wafer to make the base adhere tothe semiconductor wafer, whereby when the surroundings of theexfoliation portion are evacuated the silicone is sunk in the recessesso as to be peeled off from the semiconductor wafer. The exfoliationportion of the carrier may be a net or an irregular surface formed onthe base.

[0024] In addition, the carrier employed in the semiconductor waferprocessing method according to the invention has its base made of atransparent material and its adhesive member made of a UV cure-typeadhesive of which the adhesion is reduced or lost by ultraviolet raysradiated through the base so that the carrier can be peeled off from thesemiconductor wafer.

[0025] Also, the adhesive member employed in the semiconductor waferprocessing method according to the invention is made of a temperatureactivation type adhesive of which the adhesion is reduced or lost bytemperature change so that the carrier can be peeled off from thesemiconductor wafer. The temperature activation type adhesive of thiscarrier may have such a characteristic that its adhesion is reduced orlost at a low temperature.

[0026] The adhesive member employed in the semiconductor waferprocessing method according to the invention is a liquid that acts as anadhesive in such a manner that the semiconductor wafer and the base aremade in intimate contact with each other by the interfacial forceexerted therebetween and that the semiconductor wafer is peeled off fromthe base by ultrasonic waves.

[0027] The base of the carrier should be made of an acid-resistantmaterial, for example, compacted fibrous fluororesin.

[0028] Thus, since the semiconductor wafer thinning process is performedon the wafer composite formed by bonding the semiconductor wafer to thecarrier, any cracks can be prevented from occurring even with no strictcare when the semiconductor wafer is thinned. In addition, since thereduction of the rigidity of the thinned semiconductor wafer can becompensated for by the carrier so that release of the stress in thepassivation film is prevented, the semiconductor wafer is not warped.Thus, the semiconductor wafer can be stably processed to be extremelythin.

[0029] Moreover, since the wafer composite can be handled in the sameway as the semiconductor wafer having a normal thickness beforethinning, any cracks can be prevented form occurring on thesemiconductor wafer even with no strict care, and the work for thinningcan be made with ease.

[0030] In addition, since the carrier of the wafer composite issupported so that no unnecessary stress is exerted on the semiconductorwafer, any warp does not occur, and thus the semiconductor can bethinned with high quality.

[0031] If the semiconductor wafer is fixed to the base by the suctionpad, the carrier is not necessary to be discarded after use, and can besimplified in its construction, and thus the semiconductor wafer can bethinned at low cost.

[0032] If the wafer composite is formed by attaching the semiconductorwafer to the base to overhang from the carrier and spin-coated with anetchant while gas is continuously blown against this wafer composite,the etchant can be surely prevented from flowing around the outerperipheral side into the main surface, thus the circuit elements beingnot damaged.

[0033] If the wafer composite is so formed that the outer periphery ofthe semiconductor wafer does not overhang from the carrier, the etchantis prevented from flowing around the peripheral side into the mainsurface, and thus it is not necessary to blow gas against the wafercomposite. Moreover, since the thinned semiconductor wafer does notoverhang from the carrier, the wafer composite can be easy to handle.Also, since all the main surface of the semiconductor wafer is coveredby the carrier so that it is shielded from the external atmosphere, therear surface of the semiconductor wafer can be etched even by dipping.

[0034] If an IC card is produced by using semiconductor chips that areproduced by dicing the thinned semiconductor wafer, the IC card can bemade thinner than that of the conventional one.

[0035] If the thickness of the adhesive member provided on the base ismade equal to or larger than the height of the bumps formed on thesemiconductor wafer, all the carrier is made in intimate contact withthe semiconductor wafer so that both are not peeled off from each other.Also, if the semiconductor chips are directly mounted on the cardsubstrate from the dicing sheet, the additional moving operation for thesemiconductor chips can be omitted, thus throughput can be improved.

[0036] The peeling operation after thinning can be simplified by takingthe vacuum suction structure of the carrier for sucking thesemiconductor wafer or by using the adhesive member formed of thepeeling portion and the adhesive sheet or formed of UV cure-typeadhesive or temperature activation adhesive. Moreover, since thesemiconductor wafer is always kept flat along the base, the warp of thesemiconductor wafer can be effectively suppressed.

[0037] Since the carrier formed of an reversible temperature activationtype adhesive can be repeatedly used in the thinning process, thethinned semiconductor wafer can be mass-produced at low cost.

[0038] Since the carrier having the base made of an acid resistantmaterial can be repeatedly used in the thinning process, the thinnedsemiconductor wafer can be mass-produced at low cost.

[0039] Since the base may be made of compacted fibrous fluororesinhaving a feature of resistance against acid, it is possible to usevarious different adhesives such as-temperature activation type adhesivewith weak adhesion to the base.

BRIEF DESCRIPTION OF DRAWINGS

[0040]FIG. 1 is a plan view of the carrier used in the semiconductorwafer thinning process of one embodiment of the invention, FIG. 2 is across-sectional view taken along a line II-II in FIG. 1, FIG. 3 showspart of the semiconductor wafer processing procedure using the carrierof FIG. 1, FIG. 4 is another part of the procedure using the carrier ofFIG. 1 after the operation of FIG. 3, FIG. 5 is a schematic diagram ofthe etching apparatus used in the semiconductor wafer thinning processaccording to the invention, FIG. 6 shows another part of the procedureusing the carrier after the operation of FIG. 4, FIG. 7 shows anotherpart of the procedure using the carrier after the operation of FIG. 6,FIG. 8 shows another part of the procedure using the carrier of FIG. 1after the operation of FIG. 7, FIG. 9 shows another part of theprocedure using the carrier of FIG. 1 after the operation of FIG. 8,FIG. 10 shows another part of the procedure using the carrier of FIG. 1after the operation of FIG. 9, FIG. 11 is a plan view of the carrierused in the semiconductor wafer thinning process according to anotherembodiment of the invention, FIG. 12 is a cross-sectional view takenalong a line XII-XII in FIG. 11, FIG. 13 is a plan view of the carrierused in the semiconductor wafer thinning process according to stillanother embodiment of the invention, FIG. 14 is a cross-sectional viewtaken along a line XIV-XIV in FIG. 13, FIG. 15 is a plan view of thecarrier used in the semiconductor wafer thinning process according tostill another embodiment of the invention, FIG. 16 is a cross-sectionalview taken along a line XVI-XVI in FIG. 15, FIG. 17 is a plan view ofthe carrier used in the semiconductor wafer thinning process accordingto still another embodiment of the invention, FIG. 18 is across-sectional view taken along a line XVIII-XVIII in FIG. 17, FIG. 19is a plan view of the carrier used in the semiconductor wafer thinningprocess according to still another embodiment of the invention, FIG. 20is a cross-sectional view taken along a line XX-XX in FIG. 19, FIG. 21is a plan view of the carrier used in the semiconductor wafer thinningprocess according to still another embodiment of the invention, FIG. 22is a cross-sectional view taken along a line XXII-XXII in FIG. 21, FIG.23 shows part of the semiconductor wafer processing procedure using thecarrier of FIG. 21, FIG. 24 shows another part of the semiconductorwafer processing procedure using the carrier of FIG. 21 after theoperation of FIG. 23, FIG. 25 shows another part of the semiconductorwafer processing procedure using the carrier of FIG. 21 after theoperation of FIG. 24, FIG. 26 shows another part of the semiconductorwafer processing procedure using the carrier of FIG. 21 after theoperation of FIG. 25, FIG. 27 shows another part of the semiconductorwafer processing procedure using the carrier of FIG. 21 after theoperation of FIG. 26, FIG. 28 shows another part of the semiconductorwafer processing procedure using the carrier of FIG. 21 after theoperation of FIG. 27, FIG. 29(a) illustrates the state of the bondedsemiconductor wafer and carrier, FIG. 29(b) illustrates the state of theseparated semiconductor wafer and carrier, FIG. 30 shows another part ofthe semiconductor wafer processing procedure using the carrier of FIG.21 after the operation of FIG. 28, FIG. 31 shows part of thesemiconductor wafer processing procedure according to still anotherembodiment of the invention, FIG. 32 shows another part of the procedureafter the operation of FIG. 31, FIG. 33 shows another part of theprocedure after the operation of FIG. 32, FIG. 34 shows another part ofthe procedure after the operation of FIG. 33, FIG. 35 shows another partof the procedure after the operation of FIG. 34, FIG. 36 shows anotherpart of the procedure after the operation of FIG. 35, FIG. 37 showsanother part of the procedure after the operation of FIG. 36, FIG. 38 isa plan view of the carrier used in the semiconductor wafer thinningprocess according to still another embodiment of the invention, FIG. 39is a cross-sectional view taken along a line XXXIX-XXXIX in FIG. 38,FIG. 40 is a cross-sectional view of the carrier used in thesemiconductor wafer thinning process according to still anotherembodiment of the invention, FIG. 41 shows part of the semiconductorwafer processing procedure according to still another embodiment of theinvention, FIG. 42 shows another part of the procedure following theoperation of FIG. 41, FIG. 43 shows another part of the procedurefollowing the operation of FIG. 42, FIG. 44 shows another part of theprocedure following the operation of FIG. 431 FIG. 45 shows another partof the procedure following the operation of FIG. 44, FIG. 46 showsanother part of the procedure following the operation of FIG. 45, FIG.47 shows another part of the procedure following the operation of FIG.46, FIG. 48 shows another part of the procedure following the operationof FIG. 47, FIG. 49 shows another part of the procedure following theoperation of FIG. 48, FIG. 50 shows another part of the procedurefollowing the operation of FIG. 49, FIG. 51 shows another part of theprocedure following the operation of FIG. 50, FIG. 52 shows another partof the procedure following the operation of FIG. 51, FIG. 53 showsanother part of the procedure following the operation of FIG. 52, FIG.54 shows another part of the procedure following the operation of FIG.53, FIG. 55 is an enlarged plan view of the chip electrode portion ofthe semiconductor wafer of FIG. 41, FIG. 56 is a cross-sectional viewtaken along a line C₁-C₁, FIG. 57 shows the details of FIG. 48, FIG. 58is a plan view of the internal structure of the IC card producedaccording to this embodiment, FIG. 59 is a cross-sectional view takenalong a line C₂-C₂, FIG. 60 is an enlarged cross-sectional view ofportion A of FIG. 59, and FIG. 61 is an enlarged cross-sectional view ofportion B of FIG. 60.

BEST MODE FOR CARRYING OUT THE INVENTION

[0041] Preferred embodiments of the invention will be described indetail with reference to the accompanying drawings. In all the figuresuseful for the embodiments, like elements are identified by the samereference numerals, and will not be repeatedly described.

[0042]FIG. 1 is a plan view of the carrier used in the semiconductorwafer thinning process according to one embodiment of the invention,FIG. 2 is a cross sectional view taken along the line II-II in FIG. 1,FIG. 3, FIG. 4 and FIGS. 6 to 10 are flow diagrams of the semiconductorwafer processing procedure using the carrier of FIG. 1, and FIG. 5 is aschematic diagram of the etching apparatus used in the semiconductorwafer thinning process.

[0043] The carrier 1 depicted in FIGS. 1 and 2 has a plate-like shape inorder for the semiconductor wafer 2 (shown in FIG. 3 and other figures)to be stuck and held on the carrier to form the wafer composite 10 (asshown in FIG. 3 and other figures). This carrier 1 is formed of a base 1a and an elastically flexible suction pad (adhesive member) 1 b providedon one surface of the base 1 a. The base 1 a formed in a disk along theshape of the semiconductor wafer 2 is made of, for example, fluororesin,glass plate or epoxy resin which has resistance to acid. The suction pad1 b to which the semiconductor wafer 2 is stuck is made of, for example,soft rubber having a size enough to absorb, or adhere to substantiallyall region of one surface of the semiconductor wafer 2. In thisembodiment and the following embodiments, the base la constituting thecarrier 1 is preferably made of a material having resistance to acid asdescribed above in order that it can be prevented from changing inquality by an etchant L (FIGS. 5, 6). In addition, in order that thesemiconductor wafer 2 can be prevented from being broken by the actionof concentrated stress by the supporting pins of the etching apparatuson the supported locations of the semiconductor wafer 2 as will bedescribed later, the diameter of the base 1 a is designed to beslightly, for example, about 10 μm larger than the semiconductor wafer2.

[0044] The semiconductor wafer 2 stuck on the suction pad 1 b is groundto be thin by the following process.

[0045] First, the rear surface of the semiconductor wafer 2, after thecompletion of the pretreatment process up to the electric examinationfor the circuit elements formed on the main surface, is ground to athickness of, for example, about 250 μm with a diamond grindstone orabrasive grains. In this case, immediately the thinning processdescribed later may be performed without this preliminary process.

[0046] Then, the semiconductor wafer 2, under the condition that itsrear surface having no circuit elements is directed to the outside, oropposite to the carrier 1, is pressed against the carrier 1 as shown inFIG. 3. When a light weight is loaded uniformly on the entire surface ofthe semiconductor wafer 2, the suction pad 1 b is elastically deformedso that the volume of the pad closed by the wafer 2 is decreased todischarge the internal air. When the load is removed from the wafer 2,the adhesion pad 1 b intends to be restored by itself to the originalshape. As a result, the reduced volume expands somewhat close to theoriginal volume, but air is prevented from flowing into the pad by thewafer 2 that is made in intimate contact with the pad. Consequently, apressure-reduced state is created within the suction pad 1 b, so thatthe wafer 2 adheres by suction to the carrier 1. Thus, the wafercomposite 10 is formed (FIG. 4). While in this embodiment thesemiconductor wafer 2 and carrier 1 constituting the wafer composite 10are equal in their diameters as depicted in FIG. 4, the wafer 2 may havea smaller diameter than the carrier 1 or may have a larger diameter thanthat as described later.

[0047] After the completion of wafer composite 10, a plurality of suchwafer composites with their wafers 2 up are enclosed in a cassette case20 a (FIG. 5), and carried to the etching process.

[0048]FIG. 5 shows the etching apparatus for the wafer composite 10. Theetching apparatus is a spinning-type etcher which coats an etchant L byspinning on the surface of the semiconductor wafer 2. This etchingapparatus includes a loader 30 having the cassette case 20 a, a workingstage 50 on which the wafer composite 10 being processed is placed, andan unloader 40 having a cassette case 20 b in which the processed wafercomposite 10 is enclosed. Also, it has a handler 60 for carrying thewafer composite 10 from the loader 30 to the working stage 50, and fromthe working stage 50 to the unloader 40. The wafer composite 10 iscarried with its rear surface lifted by this handler 50. Because aninert gas such as N₂ gas, or air is blown from below against the wafercomposite placed on the working stage 50, an air spout 70 is providedbeneath the working stage 50. In addition, supporting pins 80 areprovided to grip the wafer composite 10 at, for example, three locations120 degrees spaced along the peripheral edge of the stage 50. Thesupporting pins 80 can be rotated around the working stage 50 by a motornot shown, and thus the wafer composite 10 is rotated around itsrotating axis by the supporting pins 80. A nozzle 90 from which theetchant L is dropped on the semiconductor wafer 2 is further providedabove the working stage 50.

[0049] The handler 60 picks up one of the wafer composites 10 from thecassette case 20 a that has been set in the loader 30 of the etchingapparatus, and loads it on the working stage 50 with its wafer 2 sideup. Here, since the handler 60 carries the wafer composite 10 with itsrear surface (namely, base 1 a side) lifted, such a shock as to occurwhen the semiconductor wafer 2 side sucked by vacuum is carried is notadded to the semiconductor wafer 2, and particularly the semiconductorwafer 2 can be prevented from being cracked after the thinning process.

[0050] After loading the semiconductor wafer on the working stage 50, N₂gas, for instance, is blown from the gas spout 70 against the wafercomposite 10, to slightly float it from the stage 50, and it is grippedby the supporting pins 80 when floated. While the N₂ gas is beingcontinuously blown against the wafer composite 10, the wafer composite10 is rotated at a rate ranging from a few tens of turns to severalthousand turns, and the etchant L is dropped from the nozzle on thesemiconductor wafer 2, thus thinning it as shown in FIG. 6. For assuringthe flatness after etching, it is desired that when the etchant L isdropped, the nozzle 90 be moved at a constant speed up to the outerperipheral edge through the center of the semiconductor wafer 2 whilethe distance between the nozzle and the wafer is maintained constant.The etching speed of the dropped etchant L is selected to be, forexample, 30 μm/min, and etching time is chosen to be, for example, about400 seconds. In order that undesired vibration due to the high-speedrevolution is prevented from occurring, not to wave the etchant Lcausing uneven etching or not to detach the wafer 2 from the supportingpins 80, the rotation center is made coincident with the center of thewafer 2. In addition, although the constituents of etchant L to bechosen are dependent on the purpose of etching, it is desired that, inthis embodiment for thinning, the etching rate be selected to be as highas 10 μm/min to 100 μm/min. Moreover, when greater importance isattached to the flatness, the etching process may be divided into twosteps so that the second etching step can be performed with a loweretching rate one of etchant L. While in this embodiment the etchant L isa mixture of fluoric acid, nitric acid and phosphoric acid, it may beadded with a surface active agent for controlling the reaction.

[0051] In this way, the semiconductor wafer 2 of the wafer composite 10is etched to be thin up to a thickness of about 50 μm as shown in FIG.7. In this case, the thickness is not limited to 50 μm, but may bearbitrarily selected. After etching, the semiconductor wafer 2 is rinsedwith pure water, and dried by rotating it at a high speed of 1000 to3000 rpm.

[0052] After the thinning process, the wafer composite 10 is unloadedfrom the working stage 50 by the handler 60, and carried into thecassette case 20 b for unloader that is provided in the unloader 40.These processing steps are performed for each of all the wafercomposites 10 housed in the cassette case 20 a of the loader 30. Afterthe processed wafer composites are placed in the cassette case 20 b forunloader, the cassette case 20 b is taken out from the etchingapparatus.

[0053] Then, each wafer composite 10 is drawn out from the cassette case20 b, and stuck on the dicing tape 4 with a ring 3 attached in such amanner that as illustrated in FIG. 8 the rear surface of the wafer 2 canbe cemented onto the adhesive surface as in the conventional attachmentof wafer 2 on tape. The dicing tape 4 used is formed of, for example, abase made of PET (polyethylene terephthalate), vinyl chloride, polyesteror polyethylene, and an adhesive of acrylic polymer coated on the base.The base and adhesive may be other materials. The dicing tape may be ofthe self-adhesive type in which the base itself has adhesion.

[0054] After attaching the wafer composite onto the dicing tape 4, apeeling jig 5 is used to peel off the carrier 1 from the semiconductorwafer 2. Thus, the semiconductor wafer 2 50 μm thick remains stuck tothe dicing tape 4 (FIG. 10). Under this condition, the semiconductorwafer 2 can be diced into individual semiconductor chips. After dicing,the semiconductor chip or chips are mounted on an IC card through, forexample, an anisotropically conductive connection film.

[0055] According to the semiconductor wafer 2 processing technique ofthis embodiment, since the semiconductor wafer 2 is stuck to the carrier1 to form the wafer composite 10 which is then handled for the wafer 2to be thinned, cracks and warps can be prevented without strict care,and the semiconductor wafer 2 can be stably thinned up to a very smallthickness of, for example, 50 μm.

[0056] In addition, since the thinned semiconductor wafer 2 can behandled as if it were a thick semiconductor wafer before thinning, thesemiconductor wafer 2 can be prevented from cracking even without greatcare, and thus it is easy to work for thinning.

[0057] Moreover, since the carrier 1 of the wafer composite 10 is heldat different locations by the supporting pins 80, the semiconductorwafer 2 can be prevented from warping due to the stress by thesupporting pins 80, and thus it can be thinned with good qualityfinishing.

[0058] Furthermore, since the semiconductor wafer is fixed through thesuction pad 1 b to the base 1 a, useless throwing away of tape afteruse, for instance, can be omitted unlike the case of fixing on tape, andthe structure of the carrier 1 can be simplified, thus the semiconductorwafer 2 being thinned at low cost.

[0059] By making the base 1 a of an acid-resistant material, it ispossible to repeatedly use the carrier 1, so that the semiconductorwafer 2 can be mass-produced at low cost.

[0060]FIG. 11 is a plan view of the carrier in another embodiment of thesemiconductor wafer thinning process according to the invention. FIG. 12is a cross-sectional view taken along the line XII-XII in FIG. 11.

[0061] As illustrated, the carrier 1 according to this embodiment hasthe suction pad 1 b formed in a ring shape along the outer peripheraledge of the semiconductor wafer.

[0062] According to this carrier 1, since the holding force due to thevacuum of suction pad 1 b is exerted only on the outer periphery of thesemiconductor wafer, not the inner region, it is possible to suppressthe warp in the semiconductor wafer due to the stress on the innersurface region.

[0063]FIG. 13 is a plan view of the carrier used in still anotherembodiment of the semiconductor wafer thinning process according to theinvention. FIG. 14 is a cross-sectional view taken along the lineXIV-XIV in FIG. 13.

[0064] The carrier 1 in this embodiment has a plurality of suction pads1 b provided over all area of one side of the base 1 a. Therefore, thesemiconductor wafer can be supported at a plurality of locations bythese suction pads 1 b.

[0065] Thus, even if some ones of the plurality of suction pads 1 b arelost in their suction forces by deterioration or deformation, it isassured that the semiconductor wafer can be supported by the remainingones 1 b.

[0066]FIG. 15 is a plan view of the carrier used in still anotherembodiment of the semiconductor wafer thinning process according to theinvention. FIG. 16 is a cross-sectional view taken along the lineXVI-XVI in FIG. 15.

[0067] The carrier 1 in this embodiment has a smaller diameter than thesemiconductor wafer 2 so that the outer peripheral edge of thesemiconductor wafer 2 is projected from the carrier 1. In other words,the semiconductor wafer 2 of the wafer composite 10 is overhanged fromthe carrier 1. In order that the supporting pins can hold the carrier 1without being in contact with the overhanged semiconductor wafer 2, pincontact projections 1 a ₁ slightly protruding outward from thesemiconductor wafer 2 are formed at three different locations facing thepins along the peripheral edge of the carrier. Such a structure as inthe overhanged semiconductor wafer 2 can be also applied to the carrier1 in other embodiments. In addition, it is of course possible that evenin the overhanging structure, the semiconductor wafer 2 may be directlysupported without the pin contact projections 1 a ₁, though it dependson the final thickness of the semiconductor wafer 2.

[0068] In addition, the base 1 a has a hollow 6 which is communicatedwith a vacuum hole 6 a, connected to a vacuum pump 7 and a circularsuction groove (adhesive member) 11 b for adhering to the semiconductorwafer 2 by vacuum suction is concentrically formed in the surface of thecarrier 1 a so that the center of the groove is coincident with thecenter of the base 1 a. The vacuum hole 6 a has a valve 8 mounted. Thisvalve 8 is usually closed, but when a nozzle 7 a of the vacuum pump 7 isinserted into the valve, the valve 8 is extended to open the vacuum hole6 a. The suction groove 11 b is not always formed in a concentric circleon the base 1 a, but may be of an arbitrary shape such as spiral shape.While the valve 8 is provided at the center of the base 1 a asillustrated in FIG. 16, it may be mounted on, for example, the outerperipheral side of the base 1 a. Moreover, the valve 8 may be of acomplicated mechanical structure or of a simple elastic type such asrubber.

[0069] First, the nozzle 7 a is inserted into the vacuum hole 6 a toopen the valve 8 of the carrier 1, and the wafer 2 is attached onto thebase 1 a while the hollow 6 is evacuated by the vacuum pump 7. Then,after enough evacuation is made until the semiconductor wafer 2 can besecurely fixed to the base 1 a, the nozzle 7 a is withdrawn from thevalve. Since the valve 8 opens the vacuum hole 6 a to permit air to flowfrom the hollow 6 to the outside while the nozzle 7 a stays inserted inthe valve, but closes the vacuum hole 6 a after the nozzle 7 a iswithdrawn from the valve, air can be prevented from flowing from theoutside into the hollow 6 so that the semiconductor wafer 2 can be stuckonto the carrier 1, thus forming the wafer composite 10.

[0070] After the wafer composite 10 is completed, the etchant L forthinning is spin-coated on the semiconductor wafer 2 of the wafercomposite by the etching apparatus shown in FIG. 5 as described in theprevious embodiment. Here, while the wafer composite 10 is beingrotated, N₂ gas, for instance, is continuously blown from below againstthe wafer composite. Since the semiconductor wafer 2 is overhanged fromthe carrier 1 as describe above, the N₂ gas is blown against thedownward outer periphery of the main surface of the semiconductor wafer2 without being blocked by this carrier 1.

[0071] After the thinning process is finished, the wafer composite isattached onto the dicing tape, and then the vacuum hole is opened sothat the pressure in the hollow 6 can be restored to the atmosphericpressure. Accordingly, the suction force of the suction groove 11 b tothe semiconductor wafer 2 is lost, thus allowing the carrier 1 to beeasily separated from the semiconductor wafer 2. Then, the semiconductorwafer 2 on the dicing tape is diced into individual semiconductor chips.

[0072] According to the semiconductor wafer 2 processing technique ofthis embodiment, since the wafer composite 10 is formed so that thesemiconductor wafer 2 is overhanged from the carrier and since theetchant L for thinning is spin-coated on the semiconductor wafer whileair is continuously blown from below against the wafer composite 10, theetchant L can be prevented from flowing around the peripheral side intothe main surface, even though a large centrifugal force cannot beachieved because of spin-coating under a low revolution rate. Therefore,the circuit elements formed on the semiconductor wafer 2 can beprotected from being damaged by the etchant.

[0073] Moreover, since the semiconductor wafer 2 is stuck by vacuumsuction onto the carrier 1 to form the wafer composite 10, and since thereduced pressure in the hollow is restored to the atmospheric pressureafter thinning so that the wafer 2 and the carrier 1 can be separated,the carrier 1 can be smoothly peeled off.

[0074] In addition, since the semiconductor wafer 2 is kept flat alongthe base 1 a, the wafer 2 can be suppressed from warp.

[0075] It was previously described that the diameter of the wafer 2 maybe smaller than or equal to that of the carrier 1 as is contrary to thisembodiment. In this case, if the outer periphery of the main surface ofthe semiconductor wafer 2 is tightly and securely cemented to thecarrier 1 without any gap, the etchant L can be prevented from flowingaround the peripheral side into the main surface. Therefore, as in thisembodiment, there is no need to spin-coat the etchant L while air iscontinuously blown against the wafer composite 10. Also, since the thinsemiconductor wafer 2 is not overhanged from the carrier 1, it is easyto handle the wafer composite 10. Moreover, since the entire mainsurface of the semiconductor wafer 2 is covered by the carrier 1 so asto be shielded from the external atmosphere, the rear surface of thesemiconductor wafer 2 can be etched to be thinned by the dipping systemin which the wafer composite 10 itself is dipped in the etchant L, notby the spinning type etcher.

[0076]FIG. 17 is a plan view of the carrier used in still anotherembodiment of the semiconductor thinning process according to theinvention. FIG. 18 is a cross-sectional view taken along the lineXVIII-XVIII in FIG. 17.

[0077] In this embodiment, suction holes 21 b are provided in additionto the suction groove 11 b given in the previous embodiment. In otherwords, the suction holes 21 b are formed in one surface of the base 1 aat a plurality of locations so as to be communicated with the vacuumhole 6 a through which the hollow 6 is connected to the vacuum pump asdoes the suction groove 11 b. The semiconductor wafer 2 is sucked by thevacuum pump 7. Therefore, separation of the semiconductor wafer 2 fromthe carrier 1 is made by restoration to atmospheric pressure.

[0078] The semiconductor wafer 2 may be combined with the carrier 1 toform the wafer composite 10 by the vacuum suction via a plurality ofsuction holes 21 b thus formed.

[0079]FIG. 19 is a plan view of the carrier used in still anotherembodiment of the semiconductor wafer thinning process according to theinvention. FIG. 20 is a cross-sectional view taken along the line XX-XXin FIG. 19.

[0080] In this embodiment, a porous member 31 b made of resin or metalis provided on one side of the base 1 a instead of the suction groove 11b given in the previous embodiment. As illustrated in FIG. 19 at A, theporous member 31 b has a number of small holes 31 b ₁ formed, which arecommunicated with the vacuum hole 6 a through the hollow 6 as shown inFIG. 20. The semiconductor wafer 2 is stuck to the carrier 1 by thevacuum suction via the small holes 31 b ₁ of the porous disk 31 b, andseparated from the carrier by restoration to atmospheric pressure.

[0081] Thus, the semiconductor wafer 2 can also be combined with thecarrier 1 to form the wafer composite 10 by the vacuum suction via theporous member 31 b.

[0082]FIG. 21 is a plan view of the carrier used in still anotherembodiment of the semiconductor wafer thinning process according to theinvention. FIG. 22 is a cross-sectional diagram taken along the lineXXII-XXII in FIG. 21. FIGS. 23 to 28, and FIG. 30 are flow diagrams ofthe semiconductor wafer working process using the carrier shown in FIG.21. FIG. 29 are diagrams useful for explaining the sucked state andseparated state between the semiconductor wafer and the carrier. In thisembodiment, because the adhesion sheet 41 b ₁ illustrated in FIG. 22 istransparent, a net (exfoliation) 41 b ₂ is seen through this adhesionsheet 41 b ₁.

[0083] The adhesion member 41 b of the carrier 1 in this embodiment isformed of the net 41 b ₂ having a plurality of small recesses and itssurface flush with that of the base 1 a, and the adhesion sheet 41 b ₁interposed between the net 41 b ₂ and the semiconductor wafer 2 (FIGS.23 to 30) so as to stick the wafer 2 to the base 1 a. The adhesion sheet41 b ₁ is made of a flexible, surface-smooth material such as a curableliquid polymer, namely, gelled silicone containing a curable component.Therefore, when a solid substance having a smooth surface such as thesemiconductor wafer 2 is placed on the adhesion sheet 41 b ₁, the entiresurfaces of the wafer 2 and adhesion sheet 41 b ₁ are made in intimatecontact with each other and fixed by interfacial adhesion. In place ofthe net 41 b ₂, the base 1 a may have an irregular surface formed as anexfoliative portion.

[0084] A through-hole 1 a ₂ is formed in the base 1 a at its center, andit is connected to the vacuum pump when the semiconductor wafer 2 andthe carrier 1 are separated as described later.

[0085] The procedure of the semiconductor wafer 2 thinning process usingthe carrier 1 will be described below. The procedure in this embodimentis substantially the same as that in the previous embodiment mentionedfirst, and thus like elements will be described briefly.

[0086] First, as illustrated in FIG. 23, the semiconductor wafer 2thinned to a certain thickness is pressed against the carrier 1. At thistime, since the presence of looseness due to extension and slack in theadhesion sheet 41 b ₁ will cause the semiconductor 2 to vibrate when itis rotated, the adhesion sheet 41 b ₁ is required to be completely incontact with the surface of the base 1 a and net 41 b ₂. When a lightweight is loaded uniformly on the entire surface of the semiconductorwafer 2, an interfacial force is exerted between the semiconductor wafer2 and the adhesion sheet 41 b ₁, causing the semiconductor wafer 2 tostick to the carrier 1, so that the wafer composite 10 can be formed(FIG. 24). This wafer composite 10 is loaded in the etching apparatusshown in FIG. 5, and the etchant L is spin-coated on the rear surface ofthe semiconductor wafer 2 of the wafer composite 10 with thesemiconductor wafer side up (FIG. 25), thereby thinning it (FIG. 26).Then, after rinsing and drying, the wafer composite 10 is attached tothe dicing tape 4 (FIG. 27), and the through-hole 1 a ₂ of the base 1 ais connected to the vacuum pump 7 so that the semiconductor wafer issucked by vacuum (FIG. 28). Thus, the semiconductor wafer 2 and adhesionsheet 41 b ₁ securely fixed face to face as illustrated in FIG. 29 at(a) are shifted to, as it were, the point-contact state since theadhesion sheet 41 b ₁ is pulled into the small recesses of the net 41 b₂ as shown in FIG. 29 at (b). After the interfacial force between bothis extremely reduced by this shift, the carrier 1 is separated from thesemiconductor wafer 2. Thus, the thinned semiconductor wafer 2 remainsstuck to the dicing tape 4 (FIG. 30). Thereafter, the semiconductorwafer 2 is diced into individual semiconductor chips.

[0087] According to the semiconductor wafer 2 processing technique ofthis embodiment, since the pressure in the surroundings of the net 41 b₂ is reduced after thinning, thus causing the adhesion sheet 41 b ₁ tobe pulled into the small recesses of the net 41 b ₂ so that thesemiconductor wafer 2 and the adhesion sheet 41 b ₁ are brought into thepoint-contact state under which the interfacial force is reduced toallow the carrier 1 to be separated from the semiconductor wafer 2, thecarrier 1 can be more easily peeled off from the semiconductor wafer 2,and thus the thin semiconductor wafer 2 can be mass-produced with highproductivity.

[0088] In addition, since the semiconductor wafer 2 can always be keptflat along the base 1 a, it is possible to suppress the warp of thesemiconductor wafer 2.

[0089] FIGS. 31 to 37 are flow diagrams of the semiconductor waferthinning process of still another embodiment according to the invention.

[0090] The carrier 1 depicted in FIG. 31 has a transparent sheet tape 52attached to the base 1 a with a transparent adhesive 53. On the surfaceof the sheet tape 52, is coated an adhesive of which the adhesion isreduced or lost by irradiating UV (ultraviolet) light 54 (FIG. 36), or aremovable UV cure-type adhesive (adhesive member) 51 b. Moreover, thebase 1 a is made of a transparent or semitransparent material throughwhich UV light 54 can penetrate, such as acrylic acid resin, or amaterial having transparency.

[0091] The procedure of the semiconductor wafer thinning process usingthis carrier 1 will be described below. The procedure of this embodimentis substantially the same as that of the embodiment mentioned first, andthus like elements will be described briefly.

[0092] First, the semiconductor wafer 2 thinned to a certain thicknessis pressed against the UV cure-type adhesive 51 b coated surface of thecarrier 1 as illustrated in FIG. 31. When a light weight is loadeduniformly on the entire surface of the semiconductor wafer 2, the UVcure-type adhesive 51 b is pressed by the semiconductor wafer 2, thusmaking the wafer 2 fixed to the carrier 1 to form the wafer composite 10(FIG. 32). Then, the wafer composite 10 is loaded in the etchingapparatus in such a manner that the rear surface of the semiconductorwafer 2 is placed up, and the semiconductor wafer is thinned by droppingthe etchant L on the rear surface of the wafer 2 while it is being spun(FIGS. 33 and 34). After rinsing and drying, the wafer composite 10 isattached to the dicing tape 4 (FIG. 35), and UV light 54 is irradiatedon the wafer composite 10 through the base 1 a (FIG. 36). The irradiatedUV light 54 penetrates the transparent base 1 a, sheet tape 52, andadhesive 53 and reaches the UV cure-type adhesive 51 b. Therefore,adhesion of the UV cure-type adhesive 51 b is reduced by the UV light54. At this time, the carrier 1 is pulled away from the semiconductorwafer 2, and thus the thinned semiconductor wafer 2 stays stuck to thedicing tape 4 (FIG. 30). Thereafter, the semiconductor wafer 2 is dicedinto individual semiconductor chips. In this case, the dicing tape 4 maybe made of a material of which the adhesion can be reduced by theirradiation of UV light. Thus, if UV light is irradiated on thesemiconductor wafer when the semiconductor chips after dicing are pickedup, the operation is easy.

[0093] According to the semiconductor wafer 2 processing technique ofthis embodiment, the peeling-off operation can be performed with ease,since UV light 54, after thinning, is irradiated on the UV cure-typeadhesive 51 b used as an adhesive for bonding the semiconductor wafer 2and the base 1 a, thus reducing its adhesion so that the carrier 1 canbe peeled off from the semiconductor wafer 2.

[0094] In addition, since the adhesion between the carrier 1 and thesemiconductor wafer 2 is reduced by the irradiation of UV light 54,there is no heat effect on a member, such as the dicing tape 4, to whichthe semiconductor wafer 2 is transferred after thinning, and thus it ispossible to increase the freedom in the semiconductor production processdesign.

[0095] Moreover, since the thickness of the wafer composite 10 can bedecreased by use of UV cure-type adhesive 51 b, the wafer composite 10can be handled like the normal-thickness semiconductor wafer withoutparticular care to the small thickness.

[0096] Also, since the semiconductor wafer 2 can always be kept flatalong the base 1 a, it is possible to suppress the warp of thesemiconductor wafer 2.

[0097]FIG. 38 is a plan view of the carrier used in the semiconductorwafer thinning process of still another embodiment according to theinvention. FIG. 39 is a cross-sectional view taken along the lineXXXIX-XXXIX in FIG. 38.

[0098] The carrier 1 in this embodiment has the base 1 a made of a PETfilm with a thickness of, for example, 188 μm, and a temperatureactivation type adhesive (adhesive member) 61 b, coated on the base 1 a,of which the adhesion is reduced or lost at a low temperature of 0° C.to 5° C. The base 1 a may be made of PET film of which the thickness is,for example, 100 μm or 250 μm, or made of, for example, plastic or glassplate other than PET film. The temperature activation type adhesive 61 bused is of the cool-off type in which the peel strength per 25-mm widthis 35 gf to 150 gf at a temperature of 10° C. to 90° C. and is reducedto 0 gf at a temperature of, about 0° C. to 5° C. However, another typemay be used in which the temperature activation point is as high asabout 15° C. depending on the environment in which it is used. Thetemperature activation type adhesive 61 b in this specification is anadhesive of which the adhesion is reduced or lost by temperature change,and it includes the cool-off type in which the adhesion is reduced at alow temperature as in this embodiment, and a warm-off type of which theadhesion is reduced at a high temperature.

[0099] In the semiconductor wafer thinning process using this carrier 1,first, the semiconductor wafer is attached onto the carrier 1 at normaltemperature to form the wafer composite, and the semiconductor wafer isthinned by the same etching process as in the previous embodiments.Then, the wafer composite is stuck on the dicing tape so that theadhesive surface adheres to the semiconductor wafer. Thereafter, thewafer composite on the tape is left in a low-temperature environmentsuch as a refrigerator for ten minutes so that the wafer composite iscooled to, for example, 3° C. Since the temperature activation typeadhesive 61 b is of the cool-off type in which the peel strength isreduced to about 0 gf at a temperature of 0° C. to 5° C. together withgreat reduction of the adhesion, the carrier 1 can be easily peeled offfrom the semiconductor wafer when the wafer composite is cooled to 3° C.

[0100] While the temperature activation type adhesive 61 b used in thisembodiment is of the cool-off type in which the adhesion is reduced at alow temperature, it may be of the warm-off type in which the adhesion isreduced at a high temperature within a temperature range in which thebase 1 a and the dicing tape are not affected by heat. In addition, ifthe dicing tape is made of a UV tape of which the adhesion is reduced bythe irradiation of UV light, the heat effect can be completelyeliminated.

[0101] According to the semiconductor wafer thinning technique of thisembodiment, the peeling-off operation can be easily performed since thecarrier 1 using the temperature activation type adhesive 61 b as abonding agent is peeled off from the semiconductor wafer when theadhesion is reduced by temperature change. In addition, since thecarrier 1 can be repeatedly used, the thinned semiconductor wafer can bemass-produced at low cost.

[0102] Moreover, since the wafer composite can be made thin by using PETfilm for the base 1 a, it can be handled like the normal-thicknesssemiconductor wafer. Also, since the cost can be reduced, the carrier 1is disposable.

[0103] Since the film-shaped base 1 a can be peeled off from thesemiconductor wafer, the separation is easier than a plate-like andsolid material. In addition, a protective tape for BG (back grinding)before etching for thinning can be used for the base 1 a.

[0104] Also, since the semiconductor wafer is always kept flat along thebase 1 a, the warp of the semiconductor wafer can be suppressed even bythe carrier 1 of this embodiment.

[0105]FIG. 40 is a cross-sectional diagram of the carrier used in thesemiconductor wafer thinning process of still another embodimentaccording to the invention.

[0106] The base 1 a of the carrier 1 according to this embodiment ismade of pressed-hard fibrous fluororesin in place of the PET filmdescribed in the above embodiment. Thus, the bonding agent such as thetemperature activation type adhesive 61 b can enter into the gaps of thefluororesin by anchor effect so as to be surely coated on the base 1 a.The bonding agent, or adhesive member may be the UV cure-type adhesive51 b mentioned in the above embodiments.

[0107] Thus, since the carrier 1 has its base 1 a made of fluororesinhaving a feature of resistance to acid, it is possible to use variousbonding agents such as the temperature activation type adhesive 61 bthat has low adhesion to the base 1 a.

[0108] FIGS. 41 to 54 are flow diagrams of an embodiment of the IC cardproduction method according to the invention. FIG. 55 is an enlargedplan view of the electrode portion of a chip of the semiconductor wafershown in FIG. 41. FIG. 56 is a cross-sectional diagram taken along theline C₁ to C₁ in FIG. 55, FIG. 57 shows the details of FIG. 48, and FIG.58 is a plan view of the internal structure of the IC card producedaccording to this embodiment. FIG. 59 is a cross-sectional diagram takenalong the line C₂ to C₂ in FIG. 58, FIG. 60 is an enlargedcross-sectional view of portion A in FIG. 59, and FIG. 61 is an enlargedcross-sectional view of portion B in FIG. 60.

[0109] In the IC production method of this embodiment, first, thesemiconductor wafer 2 having circuit elements built in the main surface,or in which the so-called wafer process is already completed, isprepared as illustrated in FIG. 41. Therefore, a passivation film 2 a(FIGS. 55 and 56) made of, for example, Si₃N₄ film is formed on the mainsurface to shield the circuit elements from the external atmosphere sothat the characteristics of the elements can be stabilized. In theillustrated example, Au (gold) bumps 2 b are formed on the chipelectrodes by, for example, electrolytic plating or vacuum evaporation.Wiring conductors 101 a (FIG. 58 and so on) on a card substrate 101(FIG. 53 and others) which will be described later are electricallyconnected through the Au bumps 2 b to the chips. In this case, the chipelectrodes may be connected to the wiring conductors by wire bondinginstead of the bumps. In addition, bumps made of other metal, such as Pb(phosphorus)/Sn (tin) bumps may be formed on the chip electrodes.

[0110]FIG. 55 shows the chip electrode of the semiconductor wafer 2. Asillustrated, the passivation film 2 a is deposited around the Au bump 2b on the chip. As shown in FIG. 56, or in the cross-sectional diagramtaken along the line C₁-C₁ in FIG. 55, the passivation film 2 aprotecting the element region A is formed of two layers: an inorganicpassivation film 2 a ₁ as an underlayer and an organic passivation film2 a ₂ as an upper layer. The inorganic passivation film 2 a ₁ is madeof, for example, 1.2 μm-thick SiN (silicon nitride) and 0.6 μm-thickSiO₂ (silicon oxide), and the organic passivation film 2 a ₂ is made of,for example, 2.3 μm-thick polyimide. On the element region A are formed,for example, an A1 electrode conductor 2 c of 0.8 μm-thickness, and anunderbump metal 2 d on the conductor 2 c. The Au bump 2 b of, forexample, 20 μm-height is formed on this underbump metal 2 d as a platedelectrode. In this embodiment, the underbump metal 2 d is made of Ti(titanium)/Pd (palladium) for increasing the adhesion and for metaldiffusion protection. It may be made of other metal, for example, TiW(titanium-tungsten), Cr (chromium) or Cu (copper).

[0111] Then, as shown in FIG. 42, a surface-protective resist 111 iscoated on the main surface of the semiconductor wafer 2, and heated. Inaddition, as shown in FIG. 43, a BG tape 112 for rear surface grindingis attached on the main surface of the semiconductor wafer 2, and therear side of the semiconductor wafer of, for example, 550 μm thicknessis ground to a thickness of, for example, 150 μm as shown in FIG. 44.Since the resist 111 is coated on the main surface of the wafer, thesurface of the semiconductor wafer 2 can be protected from contaminationby dust in the BG process.

[0112] After the semiconductor wafer 2 is thinned by the BG process, theBG tape 112 is peeled off as shown in FIG. 45, and then the resist 111is removed as shown in FIG. 46.

[0113] The carrier 1 is prepared which has the base made of, forexample, 250 μm-thick PET film and a normal adhesive (namely, not of thetemperature activation type) coated on the base. Then, as shown in FIG.47, the semiconductor wafer 2 with its rear side up is attached onto thecarrier 1 to form the wafer composite 10. The carrier 1 may be of othertypes used in the above embodiments.

[0114] Here, the thickness of the adhesive of the carrier 1 is equal tothe height of the Au bump 2 b, or 20 μm. Therefore, the adhesive actsnot only on the Au bump 2 b, but also on the passivation film 2 a on thewafer surface 20 μm lower than the Au bump 2 b. Thus, all the carrier 1is made in intimate contact with the semiconductor wafer 2 so that bothcan be prevented from being peeled off from each other. Since theadhesive adheres to the wafer surface even though its thickness exceedsthe height of the Au bump 2 b, the thickness of the adhesive may belarger than the height of the Au bump 2 b (namely, equal to or largerthan the height of the Au bump 2 b).

[0115] If the wafer composite 10 is formed, the etchant L is dropped onthe rear surface of the semiconductor wafer of the wafer composite withits wafer side up, and thinning it by spin etching to a thickness of,for example, 50 μm. Here, if the carrier were not attached to thesemiconductor wafer, the semiconductor wafer would be warped when it isthinned to such a level because the rigidity of the semiconductor wafer2 is reduced so that the residual stress in the passivation film 2 a isreleased. Particularly when the compressing stress in SiN of inorganicpassivation film 2 a ₁ and the tension stress involved with the curingcontraction of polyimide of organic passivation film 2 a ₂ are released,the surface of the semiconductor wafer 2 would be warped to haveirregularity. Thus, If the semiconductor wafer 2 is stuck to the carrier1 to form the wafer composite 10 as in this embodiment, the baseconstituting the carrier 1 reinforces the semiconductor wafer 2 tocompensate for the reduction of rigidity, and suppresses the release ofthe stress in the passivation film 2 a, with the result that the thinnedsemiconductor wafer 2 is never warped. In this embodiment, asillustrated in FIG. 48, the diameter of the semiconductor wafer 2 islarger than that of the carrier 1 so that the semiconductor wafer 2overhangs from the carrier 1. Thus, in order that the etchant L can beprevented from flowing around onto the main surface upon etching, N₂ gas(nitrogen gas) G, for instance, is blown against the lower side of thewafer composite 10.

[0116] For spin etching, an etcher 113 of, for example, pinless chucktype is used as illustrated in FIG. 57. Here, suction grooves 113 a ₁ tobe evacuated are formed in the surface of a working stage 113 a at aplurality of locations. The suction grooves 113 a ₁ are communicatedwith an evacuation groove 113 b ₁ of an evacuation tube 113 b connectedto a vacuum pump. Since the suction grooves 113 a ₁ are evacuatedthrough the evacuation groove 113 b ₁, the semiconductor wafer 2 issucked and fixed to the working stage 113 a. Therefore, although thesemiconductor wafer 2 overhangs from the working stage 113 a, it is notnecessary to support its periphery by supporting pins. Thus, the etchantL can be properly dropped on right place without staying at unnecessarylocations of supporting pins, any defects and dents can be preventedfrom locally occurring on the semiconductor wafer during etching.

[0117] Since the flowing-around problem of the etchant L mentioned abovecan be solved by strongly combining the semiconductor wafer 2 and thecarrier 1 to be in intimate contact with each other, the diameter of thesemiconductor wafer 2 may be made smaller than that of the carrier 1. Inthat case, the N₂ gas G is not necessary to be blown against the wafercomposite 10, and also other etching system such as dipping system asdescribed above can be employed for thinning the semiconductor wafer 2.

[0118] After the semiconductor wafer 2 is thinned to a thickness ofabout 50 μm, the wafer composite 10 is attached to the dicing tape 4with its semiconductor wafer 2 side up as shown in FIG. 49. Then, asillustrated in FIG. 50, the lower surface of the tape is fixed to avacuum suction table 114, and the carrier 1 is peeled off from thesemiconductor wafer 2 by peeling.

[0119] Thereafter, as shown in FIG. 51, the semiconductor wafer 2 isdivided into individual semiconductor chips P by, for example, fullcutting. As shown in FIG. 52, UV light 54 is then irradiated on the UVadhesive of the dicing tape 4, thus reducing or loosing or losing theadhesion between the dicing tape 4 and the semiconductor wafer 2.

[0120] As illustrated in FIG. 53, the card substrate 101 is set abovethe semiconductor chip P, and the semiconductor chip P is tentativelyattached by a direct transfer system onto the card substrate 101 at achip mounting location with the anisotropically conductive adhesive 116being interposed therebetween. In the direct transfer system, the cardsubstrate is stuck up from below by a sticking-up pin 114. Then, asshown in FIG. 54, the chip P is fully bonded to the card substrate by abonding tool 118 with the lower side being supported by a pedestal 117.In this bonding process, the semiconductor chip is heated and pressedagainst the card substrate.

[0121]FIG. 58 illustrates a IC card 100 formed by the card substrate 101with the semiconductor chips P thus mounted. The IC card 100 is awireless type IC card assembled by laminate system. The IC card has itscard substrate 101 surrounded by a printed coil 101 b which is formed ina ring shape along the periphery of the IC substrate and which serves asan antenna for receiving an external signal and transmitting an internalsignal. The IC card has also a wiring conductor 101 a formed extendingfrom the printed coil 101 b. The wiring conductor 101 a connects theprinted coil 101 b and the semiconductor chips P, so that signals aretransmitted and received between the semiconductor chips P havingvarious functions and the external.

[0122] The members of the IC card 100 are laminated with an adhesive asshown in FIG. 59. In other words, a spacer 102 with recesses providedfor receiving the printed coil 101 b, wiring conductor 101 a and mountedsemiconductor chips P is bonded face to face to the chip-mounded side ofthe card substrate 101, so that the spacer 102 is flush with thesemiconductor chips P. In addition, a thickness correcting sheet 103 isattached to the spacer 102 so as to adjust thickness to bring thesemiconductor chips P such as IC chips and capacitor chips to thebending neutral point of the IC card 100 (the bending neutral point isthe center of the thickness of the IC card 100 if the members of bothsides of the semiconductor chip P are all equal). When the IC card 100is bent, the compressing force and tension exerted on the semiconductorchips P can be relieved by this thickness correcting sheet. Moreover,decorated exterior plates 104 a, 104 b that serve as the front and rearsurfaces of the IC card 100 are respectively bonded on both sides of thelaminate of card substrate 101, spacer 102 and thickness correctingsheet 103. In this embodiment, the card substrate 101, thicknesscorrecting sheet 103 and decorated exterior plates 104 a, 104 b are madeof PFT.

[0123]FIG. 60 is an enlarged view of portion A of FIG. 59. In thechip-mounted region of the IC card 100, the Au bumps 2 b areelectrically connected to the wiring conductor 101 a through theanisotropically conductive adhesive 116 and by its adhesion so that thesemiconductors P are mounted on the card substrate 101. Also, thethickness correcting sheet 103 is bonded to the card substrate 101 withthe spacer 102 interposed there-between. FIG. 61 is an enlarged view ofportion B of FIG. 60. The anisotropically conductive adhesive 116 isformed by an adhesive 116 b and conductive particles 116 a each of whichis formed of, for example, a plastic ball of about 5 μm-diameter with anAu coating. Part of the conductive particles 116 a of theanisotropically conductive adhesive 116 is crushed between the Au bump 2b and the wiring conductor 101 a. Thus, the Au bump 2 b and the wiringconductor 101 a can be electrically connected through the crushedconductive particles 116 a.

[0124] According to the IC card 100 production method of thisembodiment, since the carrier 1 and the semiconductor wafer 2 arecombined into the wafer composite 10 of which the semiconductor wafer 2is then thinned to a thickness of, for example, 50 μm without any crackand warp and diced into semiconductor chips P which are used in theassembly process for the IC card 100, the IC card 100 can be madethinner.

[0125] The present invention is not limited by the specific embodimentspreviously mentioned in detail, but is capable of various changes andmodifications without departing the scope of the invention.

[0126] For example, the base 1 a may be molded out of fluororesin, glassplate or epoxy resin, and the suction pad 1 b may be a liquid such aswater. In this case, the interfacial force is exerted between thesemiconductor wafer 2 and the base 1 a so that both materials can bebonded together, and in order to peel the carrier 1 from thesemiconductor wafer 2, ultrasonic wave is applied to the wafercomposite.

[0127] Industrial Applicability

[0128] The semiconductor wafer processing technique of the invention isuseful for the application to the semiconductor chips incorporated inultra-thin type electronic devices such as IC cards.

1. A semiconductor wafer processing method comprising: a first step ofpreparing a plate-like carrier formed of a base and an adhesive memberprovided on one surface of said base; a second step of bonding asemiconductor wafer to said carrier in such a manner that a rear surfaceof said wafer with no circuit elements formed therein is opposite tosaid carrier to form a wafer composite; and a third step of holding saidwafer composite with said semiconductor wafer up and spin-coating anetchant on the rear surface of said semiconductor wafer thereby to thinsaid semiconductor wafer.
 2. A semiconductor wafer processing methodaccording to claim 1, wherein the diameter of said semiconductor waferis larger than that of said carrier so that all the periphery of saidsemiconductor overhangs from said carrier in said wafer composite, andsaid semiconductor thinning process at the third step is performed whilegas is continuously blown from below against said wafer composite.
 3. Asemiconductor wafer processing method according to claim 1, wherein thediameter of said semiconductor wafer is equal to or smaller than that ofsaid carrier so that the periphery of said semiconductor wafer does notoverhang from said carrier in said wafer composite.
 4. A semiconductorwafer processing method according to claim 1, further comprising: afourth step of bonding to a dicing sheet the thinned rear surface ofsaid semiconductor wafer of said wafer composite processed at said thirdprocess, and peeling off said carrier from said wafer composite; and afifth step of dicing said semiconductor wafer on said dicing sheet intoindividual semiconductor chips.
 5. A semiconductor wafer processingmethod comprising: a first step of preparing a semiconductor wafer witha passivation film formed on its main surface in which circuit elementsare built up; a second step of preparing a plate-like or film-likecarrier formed of a base and an adhesive member provided on one surfaceof said base; a third step of bonding said semiconductor wafer to saidcarrier in such a manner that a rear surface of the wafer with nocircuit elements formed therein is opposite to said carrier to form awafer composite; and a fourth step of holding said wafer composite withsaid semiconductor wafer up and spin-coating an etchant on the rear sideof said semiconductor wafer thereby to thin said semiconductor wafer. 6.A semiconductor wafer processing method according to claim 5, furthercomprising: a fifth step of bonding to a dicing sheet the thinned rearsurface of said semiconductor wafer of said wafer composite processed atsaid fourth step and peeling off said carrier from said wafer composite;and a sixth step of dicing said semiconductor wafer on said dicing sheetinto individual semiconductor chips.
 7. An IC card producing methodcomprising: a first step of preparing a plate-like carrier formed of abase and an adhesive member provided on one surface of said base; asecond step of bonding a semiconductor wafer to said carrier in such amanner that a rear surface of said wafer with no circuit elements formedtherein is opposite to said carrier to form a wafer composite; a thirdstep of holding said wafer composite with said semiconductor wafer upand spin-coating an etchant on the rear surface of said semiconductorwafer thereby to thin said semiconductor wafer. a fourth step of bondingto a dicing sheet the thinned rear surface of said semiconductor waferof said wafer composite processed at said third process and peeling offsaid carrier from said wafer composite; a fifth step of dicing saidsemiconductor wafer on said dicing sheet into individual semiconductorchips; a sixth step of reducing the adhesion of said dicing sheet; aseventh step of mounting one or ones of said semiconductor chips on acard substrate at a chip-mounting location or at different chip-mountinglocations; and an eighth step of producing an IC card by using said ICsubstrate with said semiconductor chip or chips mounted.
 8. An IC cardproducing method comprising: a first step of preparing a semiconductorwafer with a passivation film formed on its main surface in whichcircuit elements are built up; a second step of preparing a plate-likecarrier formed of a base and an adhesive member provided on one surfaceof said base; a third step of bonding a semiconductor wafer to saidcarrier in such a manner that a rear surface of said wafer with nocircuit elements formed therein is opposite to said carrier to form awafer composite; a fourth step of holding said wafer composite with saidsemiconductor wafer up and spin-coating an etchant on the rear surfaceof said semiconductor wafer thereby to thin said semiconductor wafer; afifth step of bonding to a dicing sheet the thinned rear surface of saidsemiconductor wafer of said wafer composite processed at said fourthstep and peeling off said carrier from said wafer composite; a sixthstep of dicing said semiconductor wafer on said dicing sheet intoindividual semiconductor chips; a seventh step of reducing the adhesionof said dicing sheet; an eighth step of mounting one or ones of saidsemiconductor chips on a card substrate at a chip-mounting location orat different chip-mounting locations; and a ninth step of producing anIC card by using said IC substrate with said semiconductor chip or chipsmounted.
 9. An IC card producing method according to claim 7, whereinsaid semiconductor wafer has bumps formed at the chip electrodes, andthe thickness of said adhesive member provided on said base is equal toor larger than the height of said bumps.
 10. An IC card producing methodaccording to claim 7, wherein at said seventh step said semiconductorchip or chips are directly mounted on said card substrate from saiddicing sheet.
 11. A carrier employed in the semiconductor waferprocessing method of claim 1, wherein said adhesive member comprises anelastically flexible suction pad for sucking said semiconductor wafer byvacuum.
 12. A carrier according to claim 11, wherein said suction padhas a size enough to suck substantially all region of one side of saidsemiconductor wafer.
 13. A carrier according to claim 11, wherein saidsuction pad is formed in a ring shape along the outer periphery of saidsemiconductor wafer.
 14. A carrier according to claim 11, wherein saidsuction pad comprises a plurality of suction pads over all region of onesurface of said base, so that said semiconductor wafer can be supportedby said suction pads at a plurality of different locations.
 15. Acarrier employed in the semiconductor wafer processing method of claim1, wherein said adhesive member comprises a suction groove that isformed in said base to be communicated with a vacuum hole connected to avacuum pump so that said semiconductor wafer can be sucked by negativepressure and peeled off from said carrier by restoring said groove toatmospheric pressure.
 16. A carrier employed in the semiconductor waferprocessing method of claim 1, said adhesive member comprises suctionholes that are provided in one surface of said base at a plurality oflocations to be communicated with a vacuum hole connected to a vacuumpump so that said semiconductor wafer can be sucked by evacuating saidsuction holes and peeled off from said carrier by restoring said suctionholes to atmospheric pressure.
 17. A carrier employed in thesemiconductor wafer processing method of claim 1, wherein said adhesivemember comprises a porous member that has a great number of small holesand is provided on one surface of said base for its small holes to becommunicated with a vacuum hole connected to a vacuum pump so that saidsemiconductor wafer can be sucked by evacuating said small holes andpeeled off from said carrier by restoring said small holes toatmospheric pressure.
 18. A carrier employed in the semiconductor waferprocessing method of claim 1, wherein said adhesive member includes anexfoliation portion coplanar with said base to form a plurality ofrecesses and includes gelled silicone located between said exfoliationportion and said semiconductor wafer so as to make said semiconductorwafer adhere to said base, whereby when the surroundings of saidexfoliation portion are evacuated, said silicone is sunk into saidrecesses so that the carrier is peeled off from the semiconductor wafer.19. A carrier employed in the semiconductor wafer processing method ofclaim 18, wherein said exfoliation portion is a net or an irregularsurface formed in said base.
 20. A carrier employed in the semiconductorwafer processing method of claim 1, wherein said base is made of atransparent material, and said adhesive member is a UV cure-typeadhesive of which the adhesion is reduced or lost by ultraviolet raysirradiated through said base so that said carrier can be peeled off fromsaid semiconductor wafer.
 21. A carrier employed in the semiconductorwafer processing method of claim 1, wherein said adhesive membercomprises a temperature activation type adhesive of which the adhesionis reduced or lost by temperature change so that said carrier can bepeeled off from said semiconductor wafer.
 22. A carrier according toclaim 21, wherein said temperature activation type adhesive of saidcarrier has its adhesion reduced or lost at a low temperature.
 23. Acarrier employed in the semiconductor wafer processing method of claim1, wherein said adhesive member comprises a liquid that acts as anadhesive in such a manner that said semiconductor wafer and said baseare made in intimate contact with each other by the interfacial forceexerted therebetween and that the semiconductor wafer is peeled off fromthe base by ultrasonic waves.
 24. A carrier according to claim 11,wherein said base is made of an acid-resistant material.
 25. A carrieraccording to claim 24, wherein said base is made of compacted fibrousfluororesin.